It's Spring Break now. I officially have only one more Electrical Engineering class left before I graduate, EE 478, which is the capstone for Embedded Computing taught by Dr. Peckol, who I would have had for a total of four courses during my time at the University of Washington.

This past quarter was perhaps my busiest quarter yet... I took three 400-level Electrical Engineering courses. I took EE 477/525, the VLSI capstone course in designing digital integrated circuits. The class ended up taking massive amounts of time for the projects. There were three projects in total, which amounted to over 150 hours of work each. We used the FreePDK45 design kit to lay out the first two projects, which were a 256-bit SRAM cell and a 20-bit adder.

For each of the projects, we were graded competitively on a certain Figure Of Merit (FOM), which was a number we got from multiplying several measurements of our circuit. For our first project, which was to design a 256-bit SRAM cell, the FOM was Area×Delay², which you calculate by measuring the total area taken up by the chip and multiplying it by the worst possible delay for storing data in the chip squared. The team that got the best FOM got full points for the competition portion of the project, the group with the worst FOM got no points, and everybody else was graded in between on a linear scale.

For the first project, the 256-bit SRAM, my lab partner Kaitlyn and I did pretty well, and got the second-best FOM in the class. The following image shows our final circuit, which measures 19.38 µm × 13.78 µm (267.1 µm²). For reference, the smallest size square particle a person with 20/20 vision can see is 100 µm × 100 µm, so you can fit around 35 of these cells in that area.

*Our 256-bit SRAM cell (click to zoom in)*

This SRAM consists of five distinct parts: a 5-to-32 decoder, 16 bit-line pre-chargers, 16 high-skew inverters, and 8 bit-line write drivers. With our design, we measure a maximum read delay of 1.055 ns.

For our second project, we were required to design a 20 × 20 bit adder. For our design, we designed a delay-insensitive carry-lookahead with speed-up circuitry (DICLASP) based on an IEEE article we found online. What attracted us about this specific adder design was that it implemented an O(log(log(n))) algorithm, whereas most tree adders we encountered used an O(log(n)) algorithm. We deviated a lot from the implementation used in the article, whereas we made it not self-timed, and used N-P domino logic. Looking back, that might have not been a good idea, since we found out it took an extreme amount of time to lay it out, since it required 11 unique cells. One of the only three overnighters I pulled this quarter involved starting the layout for our design at 8:00 AM with my lab partner, and not finishing the layout until 1:00 PM the next day (29 straight hours of layout). Unfortunately, our effort on this project was not worth the results, since we learned N-P domino logic is not the best choice if you have long wires in your circuit.... Anyway, here is our final project layout:

*20 × 20 bit delay-insensitive carry look-ahead adder with speedup circuitry (click to zoom)*

I feel if we had more time, we could have optimized this circuit to have a much better delay, but we ended up with a delay of 1.898 ns, area of 453 µm², and power consumption of 322 fJ per computation. We ended up having the second-worst FOM, which was Area×Power×Delay² for this project. I felt that we really chose one of the hardest designs to lay out, and if we had more time for the project, we could have done a lot better with the FOM.

By the end of this project, we felt we really didn't have much time to spend on the final project, which was a 10×10 2's compliment multiplier with modified Booth encoding, so we stuck with a static logic implementation for the entire circuit. The most time-consuming part of this project was figuring out how to do 2's compliment signed multiplication, since all the examples we were shown were for unsigned multiplication. We had to figure out on our own how to implement the partial products for signed multiplication on our own, pretty much, since there was nowhere in our text book or on the internet which explained how to do signed 2's compliment multiplication.