Unfortunately, this is one of those blog posts where nobody knows what I'm talking about, so feel free to not waste your time trying to read it.

Anyway, I took three engineering classes for Fall 2009 Quarter; EE 341 - Discrete Time Linear Systems, EE 473 - Analog Integrated Circuit Design, and EE 476 - Digital Integrated Circuit Design. In EE 341 - Discrete Time Linear Systems, you pretty much cover many of the principles needed for most audio, image, and video processing. The course pretty focuses on applications of Z-transforms (which are Laplace Transforms for discrete signals), Discrete Fourier Transforms, Discrete Time Fourier Transforms, and Discrete Time Fourier Series.

In EE 473 - Analog Integrated Circuit Design, you essentially learn how to create amplifiers using 23o nm CMOS technology. For our final project, we developed an 80-dB fully-differential amplifier with several design specifications for input and output capacitance, phase margin, power consumption, output swing, and unity-gain frequency. We used a folded-cascode topology with a common-source second stage, biased with low-voltage cascode current mirrors. The circuit also implemented common-mode feedback, which we just included as a couple resistors and an ideal op-amp, and also Miller compensation. Unfortunately, we only had one week to do the project, and we ran into a pretty time-consuming problem, but eventually we got something that met most of the specifications after a rather frustrating overnighter. We could have done better if we had a little more time.

In EE 476 - Digital Integrated Circuit Design, we worked on a 45 nm CMOS process. Our final project was to design an arbiter circuit in behavioral Verilog, then using software tools to convert the Verilog code into logic gates. We drew out a series of 9 logic gate standard cells, with which we actually drew out all the transistors and connecting metal layers, and used an automated process to convert the logic gates into a layout using standard cells. Below is our resulting integrated circuit, which measures only 15 x 15 μm², consists of 91 standard cells, for a total 362 transistors.

Here is our design for just one of the standard cells, the D-Flip Flop, which measures 1.235 x 3.23 μm². A Flip-Flop is essentially a memory storage cell, which holds one bit of information.

D Flip-Flop Schematic

Layout of the D Flip-Flop

It would take a long time to explain what's going on here. All the blue rectangles are the lowest metal layer, the pink rectangles are the second metal layer, all the red rectangles are polysilicon (used for the gates for transistors), the W's indicate the p- or n-doped wells, the triangles indicate p- or n- heavily doped regions. The layout image directly translates to the schematic above. Each of the colors represents a different mask during the manufacturing process. Since it costs well over a million dollars to manufacture an integrated circuit, we mostly relied on simulation software to test our design.

Most of the work in this quarter was learning how to use the Virtuoso design suite to design and simulate our circuits. Unfortunately, the University of Washington file servers were running extremely slow, and so we wasted a lot of time waiting for the mouse to catch up. It was also frustrating, since there were three classes all trying to use the University of Washington's only 20 Linux computers at the same time.